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module cliff_classic (
output wire ds,
output wire rd,
input wire clk,
input wire go,
input wire rst_n,
input wire ws
);
// state bits
parameter
IDLE = 3'b000, // extra=0 rd=0 ds=0
DLY = 3'b010, // extra=0 rd=1 ds=0
DONE = 3'b001, // extra=0 rd=0 ds=1
READ = 3'b110; // extra=1 rd=1 ds=0
reg [2:0] state;
reg [2:0] nextstate;
// comb always block
always @* begin
nextstate = 3'bx; // default to x because default_state_is_x is set
case (state)
IDLE: begin
if (go) begin
nextstate = READ;
end
else begin
nextstate = IDLE;
end
end
DLY : begin
if (ws) begin
nextstate = READ;
end
else begin
nextstate = DONE;
end
end
DONE: begin
begin
nextstate = IDLE;
end
end
READ: begin
begin
nextstate = DLY;
end
end
endcase
end
// Assign reg'd outputs to state bits
assign ds = state[0];
assign rd = state[1];
// sequential always block
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= IDLE;
else
state <= nextstate;
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [31:0] statename;
always @* begin
case (state)
IDLE:
statename = "IDLE";
DLY :
statename = "DLY";
DONE:
statename = "DONE";
READ:
statename = "READ";
default:
statename = "XXXX";
endcase
end
`endif
endmodule
module cliff_classic (
output reg ds,
output reg rd,
input wire clk,
input wire go,
input wire rst_n,
input wire ws
);
// state bits
parameter
IDLE = 0,
DLY = 2,
DONE = 1,
READ = 3;
reg [3:0] state;
reg [3:0] nextstate;
// comb always block
always @* begin
nextstate = 4'b0000;
case (1'b1) // synopsys parallel_case full_case
state[IDLE]: begin
if (go) begin
nextstate[READ] = 1'b1;
end
else begin
nextstate[IDLE] = 1'b1;
end
end
state[DLY] : begin
if (ws) begin
nextstate[READ] = 1'b1;
end
else begin
nextstate[DONE] = 1'b1;
end
end
state[DONE]: begin
begin
nextstate[IDLE] = 1'b1;
end
end
state[READ]: begin
begin
nextstate[DLY] = 1'b1;
end
end
endcase
end
// sequential always block
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= 4'b0001 << IDLE;
else
state <= nextstate;
end
// datapath sequential always block
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ds <= 0;
rd <= 0;
end
else begin
case (1)
nextstate[IDLE]: begin
ds <= 0;
rd <= 0;
end
nextstate[DLY] : begin
ds <= 0;
rd <= 1;
end
nextstate[DONE]: begin
ds <= 1;
rd <= 0;
end
nextstate[READ]: begin
ds <= 0;
rd <= 1;
end
endcase
end
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [31:0] statename;
always @* begin
case (1)
state[IDLE]:
statename = "IDLE";
state[DLY<;/font>]<;/font> :
statename = "DLY";
state[DONE]:
statename = "DONE";
state[READ]:
statename = "READ";
default:
statename = "XXXX";
endcase
end
`endif
endmodule
Additional GUI Features
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